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	<title>Performance Within Reach &#187; x86</title>
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	<description>Performance Within Reach</description>
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		<title>[Video] Pat Gelsinger, SVP Intel, on the motivations that drove the development of the Intel Core Microarchitecture</title>
		<link>http://unmanageability.com/index.php/2006/06/11/video-pat-gelsinger-on-the-motivations-that-drove-the-development-of-the-intel%c2%ae-core%e2%84%a2-microarchitecture/</link>
		<comments>http://unmanageability.com/index.php/2006/06/11/video-pat-gelsinger-on-the-motivations-that-drove-the-development-of-the-intel%c2%ae-core%e2%84%a2-microarchitecture/#comments</comments>
		<pubDate>Sat, 10 Jun 2006 19:32:33 +0000</pubDate>
		<dc:creator>Coder</dc:creator>
				<category><![CDATA[Itanium]]></category>
		<category><![CDATA[Performance]]></category>
		<category><![CDATA[Processor]]></category>
		<category><![CDATA[x86]]></category>

		<guid isPermaLink="false">http://codeperformance.com/index.php/2006/06/09/video-pat-gelsinger-on-the-motivations-that-drove-the-development-of-the-intel%c2%ae-core%e2%84%a2-microarchitecture/</guid>
		<description><![CDATA[Stanford talk
Pat Gelsinger discusses motivations that drove the development of the IntelÂ® Coreâ„¢ Microarchitecture, some of its most important features and the challenges that face microprocessor designers in the future.
[See video]
]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.stanford.edu/class/ee380/Abstracts/060607-EE380-Gelsinger.pdf">Stanford talk</a></p>
<blockquote><p><a href="//www.stanford.edu/class/ee380/Abstracts/060607.html">Pat Gelsinger</a> <a href="http://stanford-online.stanford.edu/courses/ee380/060607-ee380-300.asx">discusses</a> motivations that drove the development of the IntelÂ® Coreâ„¢ Microarchitecture, some of its most important features and the challenges that face microprocessor designers in the future.</p></blockquote>
<p><a href="http://stanford-online.stanford.edu/courses/ee380/060607-ee380-300.asx">[See video]</a></p>
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		<slash:comments>0</slash:comments>
<enclosure url="http://stanford-online.stanford.edu/courses/ee380/060607-ee380-300.asx" length="73" type="video/x-ms-asf" />
		</item>
		<item>
		<title>Intel Developer Forum &#8211; Keynote Webcasts</title>
		<link>http://unmanageability.com/index.php/2006/03/28/intel-developer-forum-keynote-webcasts/</link>
		<comments>http://unmanageability.com/index.php/2006/03/28/intel-developer-forum-keynote-webcasts/#comments</comments>
		<pubDate>Tue, 28 Mar 2006 09:45:37 +0000</pubDate>
		<dc:creator>Coder</dc:creator>
				<category><![CDATA[Architecture]]></category>
		<category><![CDATA[Performance]]></category>
		<category><![CDATA[Scalability]]></category>
		<category><![CDATA[x86]]></category>

		<guid isPermaLink="false">http://codeperformance.com/index.php/2006/03/28/intel-developer-forum-keynote-webcasts/</guid>
		<description><![CDATA[Intel Developer Forum &#8211; Keynote Webcasts
Intel Developer Forum

Steve Pawlowski and Ofri Wechsler: IntelÂ® Coreâ„¢ microarchitecture and Usages
Paolo A. Gargini: Intel&#8217;s Silicon R&#038;D Pipeline
The keynotes of Pat P. Gelsinger (Digital Enterprise), Sean M. Maloney (Mobility), Donald J. MacDonald (The Digital Home) and Justin R. Rattner (Opening Keynote)

]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.intel.com/idf/us/spring2006/webcast.htm">Intel Developer Forum &#8211; Keynote Webcasts</a><br />
Intel Developer Forum</p>
<ul>
<li>Steve Pawlowski and Ofri Wechsler: IntelÂ® Coreâ„¢ microarchitecture and Usages</li>
<li>Paolo A. Gargini: Intel&#8217;s Silicon R&#038;D Pipeline</li>
<li>The keynotes of Pat P. Gelsinger (Digital Enterprise), Sean M. Maloney (Mobility), Donald J. MacDonald (The Digital Home) and Justin R. Rattner (Opening Keynote)</li>
</ul>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>How much more mileage is left in x86?</title>
		<link>http://unmanageability.com/index.php/2005/12/13/how-much-more-mileage-is-left-in-x86/</link>
		<comments>http://unmanageability.com/index.php/2005/12/13/how-much-more-mileage-is-left-in-x86/#comments</comments>
		<pubDate>Tue, 13 Dec 2005 07:51:06 +0000</pubDate>
		<dc:creator>Coder</dc:creator>
				<category><![CDATA[Performance]]></category>
		<category><![CDATA[x86]]></category>

		<guid isPermaLink="false">http://codeperformance.com/index.php/2005/12/13/how-much-more-mileage-is-left-in-x86/</guid>
		<description><![CDATA[DigiTimes.com&#8216;s                       Chris Hall  inteviews AMD&#8217;s Raghuram Tupuri, GM in the Microprocessor Solutions Sector â€“ Design Engineering at AMD.
Q: The consensus within the industry is that AMD64 has clearly been a tremendous achievement for AMD and to a large extent has re-defined the competitive landscape in microprocessors. What was the design approach â€“ if you like, the design ...]]></description>
			<content:encoded><![CDATA[<p><font class="Author"><a href="http://DigiTimes.com">DigiTimes.com</a>&#8216;s </font><font class="Author">                      Chris Hall </font><font class="Author"> <a href="http://www.digitimes.com/news/a20051212PR200.html">inteviews</a> AMD&#8217;s </font><font class="H1">Raghuram Tupuri, GM in the </font>Microprocessor Solutions Sector â€“ Design Engineering at <a href="http://amd.com">AMD</a>.</p>
<blockquote cite="http://www.digitimes.com/news/a20051212PR200.html"><p><strong>Q: </strong><span style="font-style: italic">The consensus within the industry is that AMD64 has clearly been a tremendous achievement for AMD and to a large extent has re-defined the competitive landscape in microprocessors. What was the design approach â€“ if you like, the design philosophy â€“ that guided development of AMD64?</span></p>
<p><span style="font-weight: bold">A</span>: The core design philosophy is to deliver higher performance to the end user. As micro-architectural improvements are achieved, they are evaluated with respect to the end-user experience and future software needs. My own view is that we have not yet reached the limits of what can be achieved by micro-architectural changes and enhancements. As we progress in the technology, and more transistors continue to become available, we will continue to see the adoption of advanced micro-architectural techniques. We will continue to see a lot more pre-fetch, in hardware, and a lot more speculative execution, but at the same time we will be factoring in power consumption.</p>
<p><span style="font-weight: bold">Q</span>: <span style="font-style: italic">How much more mileage is left in x86? Are there any realistic alternatives, given the less than compelling performance of Intel&#8217;s IA-64 architecture and Itanium processors?</span></p>
<p><span style="font-weight: bold">A</span>: I would be surprised if, a few years down, anyone even remembers the Itanium processor. Intel now offers two 64-bit solutions, IA-64 and AMD64. I think that tells you all you need to know about the success of x84 and AMD64.</p>
<p>I think there is still quite a bit of mileage left in x86, but the actual mileage will be determined by the software base. If Iâ€™m a software vendor, what I want to focus on is developing new software and selling it to more end users. If the software needs to be ported to different processor platforms, then it is time or money deducted from the development of new algorithms or the improvement of existing programs. Given the ubiquity of x86, you only need to develop a set of binaries once, and they can then be applied in any number of instances.</p>
<p>Whatever criticisms have been leveled at x86, it remains the longest surviving instruction set. No other instruction set has had this long a lifetime. Other instruction sets have come and gone, but x86 lives on. A technologist may not like x86; it may not be the sleek instruction set everyone would like to see, but in the end, itâ€™s the end users who determine which technology will be used. The marketplace determines the acceptance of a particular instruction set.</p></blockquote>
<p class="citation"><cite><a href="http://www.digitimes.com/news/a20051212PR200.html">Leading by design: Q&#038;A with Dr. Raghuram Tupuri, AMD</a></cite></p>
]]></content:encoded>
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		</item>
		<item>
		<title>server performance problems due to Hyperthreading?</title>
		<link>http://unmanageability.com/index.php/2005/11/19/server-performance-problems-due-to-hyperthreading/</link>
		<comments>http://unmanageability.com/index.php/2005/11/19/server-performance-problems-due-to-hyperthreading/#comments</comments>
		<pubDate>Sat, 19 Nov 2005 02:51:38 +0000</pubDate>
		<dc:creator>Coder</dc:creator>
				<category><![CDATA[Misc]]></category>
		<category><![CDATA[Performance]]></category>
		<category><![CDATA[x86]]></category>

		<guid isPermaLink="false">http://codeperformance.com/index.php/2005/11/19/server-performance-problems-due-to-hyperthreading/</guid>
		<description><![CDATA[Slava Ocks, a developer working on SQL Server 2005 within Microsoft, reported similar problems in a blog posting earlier this month.&#8221;Our customers observed very interesting behaviour on high-end HT-enabled hardware. They noticed that in some cases when high load is applied SQL Server CPU usage increases significantly but SQL Server performance degrades,&#8221; wrote Ocks.Ocks then detailed testing which showed this behaviour where a system thread â€” in this case one cleaning out blocks of disk cache memory â€” is running ...]]></description>
			<content:encoded><![CDATA[<blockquote cite="http://news.zdnet.co.uk/0,39020330,39237341,00.htm"><p><a href="http://blogs.msdn.com/slavao/archive/2005/11/12/492119.aspx">Slava Ocks</a>, a developer working on SQL Server 2005 within Microsoft, reported similar problems in a blog posting earlier this month.&#8221;Our customers observed very interesting behaviour on high-end HT-enabled hardware. They noticed that in some cases when high load is applied SQL Server CPU usage increases significantly but SQL Server performance degrades,&#8221; wrote Ocks.Ocks then detailed testing which showed this behaviour where a system thread â€” in this case one cleaning out blocks of disk cache memory â€” is running at the same time as worker threads. &#8220;With Intel HT technology, logical processors share L1 &#038; L2 caches. As you would guess [this] behaviour can potentially trash L1 &#038; L2 caches,&#8221; he said.</p></blockquote>
<p class="citation"><cite><a href="http://news.zdnet.co.uk/0,39020330,39237341,00.htm">Hyperthreading hurts server performance, say developers &#8211; ZDNet UK News</a></cite></p>
<p>{Update}<br />
The <em><a href="http://news.zdnet.co.uk/0,39020330,39237341,00.htm">original</a></em> story made it to Slashdot&#8230; interesting comments in the  <a href="http://hardware.slashdot.org/comments.pl?sid=168793&#038;threshold=1&#038;mode=thread&#038;commentsort=3&#038;op=Change">discussions forum</a>. Apparently, Intel does mention the cache contention issues in their documentation.</p>
<p><a href="http://www.ocelotbob.org/">OcelotBob </a>writes:</p>
<blockquote><p>In order for there to be a true benefit to hyperthreading, either the program, the OS or the compiler needs to determine that hyperthreading is enabled, and model the code to only use less than half the cache. It&#8217;s been known that way since the beginning, and frankly, is silly that MS is scratching their heads wondering why this is.</p></blockquote>
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