Sep 27
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Intel’s vision: A teraflop on a single chip

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Intel pledges 80 cores in five years | CNET News.com
… the ultimate goal, as envisioned by Intel’s terascale research prototype, is to enable a trillion floating-point operations per second–a teraflop–on a single chip. Ten years ago, the ASCI Red supercomputer at Sandia National Laboratories became the first supercomputer to deliver 1 teraflop using 4,510 computing nodes.
Intel’s prototype uses 80 floating-point cores, each running at 3.16GHz, Justin Rattner, Intel’s chief technology officer, said in a speech following Otellini’s address. …

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Sep 27
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Performance matters again

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Intel pledges 80 cores in five years | CNET News.com
“Performance matters again,” Otellini said, disclosing that the quad-core desktop processor will deliver 70 percent faster integer performance than the Core 2 Duo, and the quad-core server processor will be 50 percent faster than the Xeon 5100 introduced in June. One reason performance didn’t matter to Intel during the last couple of years was because it was getting trounced on benchmarks at the hands of Advanced Micro Devices’ Opteron …

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Aug 25
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Whitepaper on GC tuning for Sun’s VM

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Jon Masamitsu’s Weblog : Weblog
“…basic concepts, some specifics about our GC, suggestions on tuning, and some of the latest improvements such as the parallel old collector…”
http://java.sun.com/j2se/reference/whitepapers/memorymanagement_whitepaper.pdf

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Jul 31
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Slides for presentations on performance at the 8th OSCON

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O’Reilly Open Source Convention – July, 24-28, 2006 – Portland, OR

Open Source Performance Monitoring Tools and Tricks for Java

Speaker: Matt Secoske (07/28/2006)
Download presentation files

Eight Steps to Fix Your Database Performance Problem

Speaker: Christopher Browne (07/27/2006)
Download presentation files

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Jul 4
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What’s the overhead for web services calls on salesforce.com?

1

ASPs: The Integration Challenge
The main problem with performance when using the APIs provided by ASPs is the per-call overhead. The overhead comes from latency over the Internet, transmission time, marshalling (xml/SOAP) requests on the client side and responses on the ASP side, un-marshalling (xml/SOAP) requests on the ASP side and responses on the client side, and authentication/authorization checking and other overhead at the ASP.
In accessing Salesforce.com and CRM OnDemand (both of these ASPs are located in North America, as are …

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Jun 23
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Will Dolphin let us save the compiled code cache?

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More tiered compilation
… a repository of information collected from one run and used on another run is on the list for things we want to do in Dolphin. It’s actually on the runtime groups list but we will certainly take advantage of it. There has also been talk of using annotations to give the jit a hint. This actually isn’t too popular since it is too much like “register” declarations in C. It’s only a hint and is too often …

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Jun 23
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Is OS specific interruptible I/O a Java portability headache?

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Java Portability
…this program below does nothing visible on Solaris, but prints “hello” with Sun Java SE on Linux and Windows:
public class Foo {
public static void main(String[] args) {
Thread.currentThread().interrupt();
System.out.println(“hello”);
}
}
First impressions of this program’s behavior on Solaris roughly translate to “The hell you say!” followed by “Java is broken on Solaris!” There are a number of “symptoms” of interruptible I/O that catch users off guard and in a few cases one is led to wonder if it might be best to do …

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Jun 19
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Vista improvements in performance and scalability

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Scott Dorman — Windows Vista: Kernel Changes – Shadows of Reliability, Performance and Scalability
Vista makes fewer and larger disk reads for page faults and system cache read-ahead and has removed the 64KB limit. Fewer, faster, and larger disk writes for the system page file and mapped file I/O reduce the page file fragmentation and allow a larger cluster size.
The CPU usage has also been improved by providing improvements in the concurrency management within the kernel.

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Jun 12
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It’s 2006, CMP vs. BMP?

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Musings on software » Why choose cmp
…consider the strengths in performance and reduction in development that can be added by leveraging a high-quality CMP container as opposed to developing data access logic using a BMP architecture. I guarantee you’ll be happy with the results.
Excellent post! I couldn’t agree more, the debate mirrors the one around the merits and usefulness of automatic garbage collection. Sure you can manage memory yourself, but how much are you willing to pay for that vs. …

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Jun 11
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[Video] Pat Gelsinger, SVP Intel, on the motivations that drove the development of the Intel Core Microarchitecture

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Stanford talk
Pat Gelsinger discusses motivations that drove the development of the Intel® Core™ Microarchitecture, some of its most important features and the challenges that face microprocessor designers in the future.
[See video]

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